IME CAS High-Density 3D DRAM Research Progress

Reference TimelineLast updated JAN 9
SUMMARY

Researchers at IME CAS have developed a novel capacitor-less DRAM-like memory cell (4F² dual-gate 2T0C) that achieves high density and performance without a traditional storage capacitor. This breakthrough, utilizing a self-aligned single-step process with two vertical IGZO transistors, offers multi-bit storage, fast write times, and extended data retention, making it a promising candidate for embedded and 3D-stacked memory applications. While not yet a replacement for commodity DRAM, this development signifies significant progress in overcoming the limitations of planar DRAM and paving the way for next-generation memory technologies. The ongoing research and development in 3D DRAM by various institutions and companies indicate a strong industry push towards higher density and performance memory solutions.

Timeline

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2025

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Lam Research discussed the evolution of DRAM scaling from 2D to 3D architectures, highlighting innovations like high aspect ratio etching, atomic layer deposition (ALD), and the use of molybdenum to address resistivity challenges. The company emphasized the role of stacking chips for High Bandwidth Memory (HBM) and the potential of 3D scaling to achieve unprecedented memory densities.

via allpcb.com·semiengineering.com·tomshardware.com·toteam.co.il

A breakthrough in 3D DRAM materials and architectures was reported, promising to overcome the limitations of planar DRAM. Industry projections indicated that first proof-of-concept chips were expected in late 2026, with initial markets including high-performance computing and cloud data centers. The path to mainstream adaptation for consumer electronics was forecast within 4-5 years, with major players like Samsung and Micron heavily investing in this technology.

via allpcb.com·semiengineering.com·tomshardware.com·toteam.co.il

Research presented on a 3-D nCS FeRAM architecture demonstrated its potential for high-density, energy-efficient memory integration, suitable for next-generation AI and embedded memory applications. Additionally, studies on Si/SiGe nanosheet-based CMOS technology explored stress evolution during sequential stacking, crucial for sub-3 nm technology nodes and the reliability of integrated circuits.

via allpcb.com·semiengineering.com·tomshardware.com·toteam.co.il

Researchers at imec and Ghent University achieved a significant step towards 3D DRAM by growing 120 alternating layers of silicon (Si) and silicon-germanium (SiGe) on a 300 mm wafer. This was accomplished by carefully tuning the germanium content, adding carbon to relieve stress, and maintaining uniform temperatures during deposition. This multilayer structure is crucial for vertical scaling and enabling next-generation, high-density memory devices.

via allpcb.com·semiengineering.com·tomshardware.com·toteam.co.il

Research on scaled dual-gate Indium-Gallium-Zinc Oxide (IGZO) thin-film transistors (TFTs) for two-transistor-zero-capacitance DRAM showed promise. These IGZO TFTs, scaled down to 30 nm, demonstrated excellent electrical performance and significantly longer retention times (540 seconds) compared to silicon-based DRAM. This research indicated the potential of IGZO for high-density back-end-of-line integration in emerging DRAM technology.

via allpcb.com·semiengineering.com·tomshardware.com·toteam.co.il

Samsung stated its intention to introduce an early version of 3D DRAM utilizing vertical channel transistor technology in 2025. This technology involves orienting the channel vertically within the transistor cell and surrounding it with a gate. Samsung also projected delivering an updated stacked DRAM by 2030 that would integrate all cell elements, including capacitors.

via allpcb.com·semiengineering.com·tomshardware.com·toteam.co.il

2024

1 update

A company (likely Lam Research, based on context from other sources) was in the process of building proof-of-concept (PoC) wafers for 3D DRAM. The first phase, focused on cell-level demonstration and optimization, was expected to yield wafers in 2025, with the second phase, integrating the module into a complete device, anticipated in 2026. This work aimed to address the challenges of stacking DRAM layers, particularly the capacitor component, which has been a hurdle for 3D DRAM development.

via allpcb.com·semiengineering.com·tomshardware.com·toteam.co.il

2023

1 update

Samsung announced plans to introduce a new 3D cell structure in next-generation 10 nm-class DRAM, moving away from traditional 2D layouts. The company presented research results and internal chip images at the 2023 VLSI Symposium in Japan and opened an R&D lab in Silicon Valley focused on 3D DRAM. Samsung's goal was to achieve 2025 production and scale the process node to 8-9 nm by 2027-2028.

via allpcb.com·semiengineering.com·tomshardware.com·toteam.co.il

2026

Story began · 2 months ago