3D DRAM Research and Development
Kioxia Corporation developed highly stackable oxide-semiconductor channel transistors for high-density, low-power 3D DRAM, presented on June 30, 2026, at the IEEE International Electron Devices Meeting. As of June 2026, major semiconductor companies like SK Hynix, Samsung, and Micron have moved HBM4 into high-volume production, utilizing 3D-stacked DRAM with materials like Silicon-Germanium (SiGe) to achieve speeds exceeding 2.8 terabytes per second for AI chips. Imec also unveiled a 3D implementation of charge-coupled device (CCD) memory architecture and advanced vertically stacked IGZO-based FeFETs. NEO Semiconductor announced successful proof-of-concept validation of its 3D X-DRAM technology in May 2026, aiming for higher densities and lower power consumption, while IME CAS proposed new dual-gate 4F² 2T0C memory cell architectures for increased storage density.
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July 2026 — 1 developments
Collaborative 3D-DRAM Cell Developed by Imec, Samsung, and Lam Research
Imec, KU Leuven, Samsung Electronics, and Lam Research have detailed a collaboratively developed, monolithically stackable 3D-DRAM cell utilizing an oxide-semiconductor channel. This research focuses on optimizing the 3D-DRAM architecture through process and device simulation to address scaling challenges of planar DRAM by moving to vertical stacking.
June 2026 — 4 developments
Kioxia Develops Oxide-Semiconductor Transistors for High-Density 3D DRAM
Kioxia Corporation has developed highly stackable oxide-semiconductor channel transistors that could enable the practical implementation of high-density, low-power 3D DRAM. Presented at the IEEE International Electron Devices Meeting, this technology uses vertical transistors made of oxide-semiconductors and has the potential to reduce power consumption for applications like AI servers and IoT components.
Imec Unveils 3D CCD Memory Architecture and Advances in Ferroelectric Memory
Imec has unveiled a 3D implementation of charge-coupled device (CCD) memory architecture, stacking memory cells vertically to address the 'memory wall' bottleneck in AI computing. The research hub also presented advances in vertically stacked IGZO-based ferroelectric field-effect transistors (FeFETs) for high-density memory applications.
Major Companies Ramp Up HBM4 Production in 2026 for AI Chips
Major semiconductor companies including SK Hynix, Samsung, and Micron have officially moved HBM4 into high-volume production in 2026. This new generation of memory doubles the memory highway to 2048 bits, delivering speeds exceeding 2.8 terabytes per second, which is essential for massive AI chips. The shift to 3D-stacked DRAM, utilizing materials like Silicon-Germanium (SiGe), is crucial for overcoming space constraints and enabling higher densities.
IME CAS Proposes New 3D DRAM Cell Architecture with Self-Oxidation Process
A research team from IME CAS has proposed a new dual-gate 4F² 2T0C memory cell architecture incorporating an in-situ metal self-oxidation process. This technique enables self-aligned integration of read and write transistors within the 4F² memory cell, which, combined with multi-level storage, can further boost storage density.
May 2026 — 1 developments
NEO Semiconductor validates 3D X-DRAM proof-of-concept, secures investment
NEO Semiconductor has announced the successful proof-of-concept validation of its 3D X-DRAM technology, which utilizes a vertically stacked architecture inspired by 3D NAND manufacturing techniques. This approach aims to overcome the scaling limitations of conventional DRAM, offering the potential for much higher densities and lower power consumption. The company has also secured strategic investment to further develop this next-generation memory alternative to HBM.
April 2026 — 1 developments
IME CAS Researchers Develop Novel Dual-Gate 4F² 2T0C Memory Cell for 4-bit Multi-Level Storage
Researchers at IME CAS, in collaboration with Shandong University and SAMT, have developed a novel dual-gate 4F² 2T0C memory cell architecture supporting 4-bit multi-level storage. This new architecture achieves a write time of 50 ns and data retention exceeding 300 seconds, with a threshold voltage shift below 100 mV after thermal stability tests.
November 2025 — 1 developments
Lam Research discusses DRAM scaling evolution and 3D architecture innovations
Lam Research discussed the evolution of DRAM scaling from 2D to 3D architectures, highlighting innovations like high aspect ratio etching, atomic layer deposition (ALD), and the use of molybdenum to address resistivity challenges. The company emphasized the role of stacking chips for High Bandwidth Memory (HBM) and the potential of 3D scaling to achieve unprecedented memory densities.
September 2025 — 2 developments
Samsung and Micron invest in 3D DRAM technology for high-performance computing and cloud data centers
A breakthrough in 3D DRAM materials and architectures was reported, promising to overcome the limitations of planar DRAM. Industry projections indicated that first proof-of-concept chips were expected in late 2026, with initial markets including high-performance computing and cloud data centers. The path to mainstream adaptation for consumer electronics was forecast within 4-5 years, with major players like Samsung and Micron heavily investing in this technology.
Research demonstrates 3-D nCS FeRAM potential and explores Si/SiGe nanosheet CMOS stress
Research presented on a 3-D nCS FeRAM architecture demonstrated its potential for high-density, energy-efficient memory integration, suitable for next-generation AI and embedded memory applications. Additionally, studies on Si/SiGe nanosheet-based CMOS technology explored stress evolution during sequential stacking, crucial for sub-3 nm technology nodes and the reliability of integrated circuits.
August 2025 — 1 developments
imec and Ghent University Grow 120 Si/SiGe Layers for 3D DRAM on 300mm Wafer
Researchers at imec and Ghent University achieved a significant step towards 3D DRAM by growing 120 alternating layers of silicon (Si) and silicon-germanium (SiGe) on a 300 mm wafer. This was accomplished by carefully tuning the germanium content, adding carbon to relieve stress, and maintaining uniform temperatures during deposition. This multilayer structure is crucial for vertical scaling and enabling next-generation, high-density memory devices.
May 2025 — 1 developments
Researchers demonstrate scaled IGZO TFTs for high-density DRAM with 540-second retention
Research on scaled dual-gate Indium-Gallium-Zinc Oxide (IGZO) thin-film transistors (TFTs) for two-transistor-zero-capacitance DRAM showed promise. These IGZO TFTs, scaled down to 30 nm, demonstrated excellent electrical performance and significantly longer retention times (540 seconds) compared to silicon-based DRAM. This research indicated the potential of IGZO for high-density back-end-of-line integration in emerging DRAM technology.
April 2025 — 1 developments
Samsung to introduce early 3D DRAM with vertical channel transistor technology by 2025
Samsung stated its intention to introduce an early version of 3D DRAM utilizing vertical channel transistor technology in 2025. This technology involves orienting the channel vertically within the transistor cell and surrounding it with a gate. Samsung also projected delivering an updated stacked DRAM by 2030 that would integrate all cell elements, including capacitors.
December 2024 — 1 developments
Lam Research plans 3D DRAM proof-of-concept wafers by 2025, addressing stacking challenges
A company (likely Lam Research, based on context from other sources) was in the process of building proof-of-concept (PoC) wafers for 3D DRAM. The first phase, focused on cell-level demonstration and optimization, was expected to yield wafers in 2025, with the second phase, integrating the module into a complete device, anticipated in 2026. This work aimed to address the challenges of stacking DRAM layers, particularly the capacitor component, which has been a hurdle for 3D DRAM development.
October 2023 — 1 developments
Samsung unveils 3D cell structure for next-gen 10nm-class DRAM, targets 2025 production
Samsung announced plans to introduce a new 3D cell structure in next-generation 10 nm-class DRAM, moving away from traditional 2D layouts. The company presented research results and internal chip images at the 2023 VLSI Symposium in Japan and opened an R&D lab in Silicon Valley focused on 3D DRAM. Samsung's goal was to achieve 2025 production and scale the process node to 8-9 nm by 2027-2028.